1. Field
This invention relates to fabrication of silicon carbide substrates and, more particularly, to silicon carbide substrates having epitaxial film grown thereupon.
2. Related Art
Silicon carbide, SiC, is a crystalline semiconductor material, recognized by those familiar with materials science, electronics and physics as being advantageous for wide band gap properties and also for extreme hardness, high thermal conductivity and chemical inert properties. These properties make SiC a very attractive semiconductor for fabrication of power semiconductor devices, enabling power density and performance enhancement over devices made from more common materials like silicon.
The most common forms of SiC consist of cubic or hexagonal arrangements of atoms. The stacking of Si and C layers can take on many forms, known as polytypes. The type of silicon carbide crystal is denoted by a number denoting the number of repeat units in the stacking sequence followed by a letter representing the crystalline format. For example the 3C-SiC polytype refers to a repeat unit of 3 and a cubic (C) lattice, while a 4H-SiC polytype refers to repeat unit of 4 and a hexagonal (H) lattice.
The different silicon carbide polytypes have some variations in materials properties, most notably electrical properties. The 4H-SiC polytype has the relatively larger bandgap while the 3C-SiC has a smaller bandgap, with the bandgaps for most other polytypes falling in between. For high performance power device applications when the bandgap is larger, the material is more capable, in theory, to offer relatively higher high power and thermal conductivity performance.
SiC crystals do not occur in nature and as such must be synthesized. Growth of SiC crystals can be executed by sublimation/physical vapor transport or chemical vapor deposition.
Once SiC crystals are produced, each crystal must be cut and fabricated into wafers using planar fabrication methods to fabricate semiconductor devices. As many semiconductor crystals (e.g., silicon, gallium arsenide) have been successfully developed and commercialized into wafer products, the methods to fabricate wafers from bulk crystals are known. A review of the common approaches to, and requirements for wafer fabrication and standard methods of characterization can be found in Wolf and Tauber, Silicon Processing for the VLSI Era, Vol. 1—Process Technology, Chapter 1 (Lattice Press—1986). Due to its hardness, fabrication of SiC into wafer substrates presents unique challenges compared to processing other common semiconductor crystals like silicon or gallium arsenide. Modifications must be made to the machines, and the choices of effective abrasives are beyond commonly used materials. The modifications made to common wafer fabrication techniques in order to accommodate SiC are often kept as proprietary information. However, it has been reported that substantial subsurface damage is observable on mirror polished SiC wafers, and this can be reduced or removed by using chemical enhanced mechanical polishing methods similar to that used in the silicon industry (Zhou, L., et al., Chemomechanical Polishing of Silicon Carbide, J. Electrochem. Soc., Vol. 144, no. 6, June 1997, pp. L161-L163).
In order to build semiconductor devices on SiC wafers, additional crystalline SiC films must be deposited on the wafers, so as to create the device active regions with the required conductivity value and conductor type. This is typically done using chemical vapor deposition (CVD) methods. Techniques for growth of SiC by CVD epitaxy have been published from groups in Russia, Japan and the United States since the 1970's. The most common chemistry for growth of SiC by CVD is a mixture of a silicon containing source gas (e.g., monosilanes or chlorosilanes) and a carbon containing source gas (e.g., a hydrocarbon gas). A key element to growth of low defect epitaxial layers is that the substrate surface is tilted away from the crystal axis of symmetry, to allow the chemical atoms to attach to the surface in the stacking order established by the substrate crystal. When the tilt is not adequate, the CVD process will produce three dimensional defects on the surface, and such defects will result non-operational semiconductor devices. Surface imperfections, such as cracks, subsurface damage, pits, particles, scratches or contamination will interrupt the replication of the wafer's crystal structure by the CVD process (see, for example, Powell and Larkin, Phys. Stat. Sol. (b) 202, 529 (1997)). Therefore, it is important that the polishing and cleaning processes used to fabricate the wafer minimize surface imperfections. In the presence of these surface imperfections several defects can be generated in the epitaxial films, including basal plane dislocations and cubic SiC inclusions (see for example, Powell, et. al. Transactions Third International High-Temperature Electronics Conference, Volume 1, pp. 11-3 -11-8, Sandia National Laboratories, Albuquerque, N. Mex. USA, 9-14 June 1996).
The methods of SiC epitaxy have been reviewed by G. Wagner, D. Schulz, and D. Siche in Progress in Crystal Growth and Characterization of Materials, 47 (2003) p. 139-165. Wagner discusses that SiC epitaxy can achieve favorable results if performed in a hot wall reactor, where all the surfaces of the reaction cell that are exposed to gases, including the susceptor that holds the SiC substrate, are actively heated. This is in contrast to a cold wall reactor where only the susceptor supporting the SiC substrate is actively heated, while the other surfaces are actively cooled or designed not to heat. Today there is also a so called warm wall CVD system, which is an intermediate of the hot and cold wall design, where the susceptor of the reaction cell supporting the SiC substrate is actively heated, and top and side surfaces of the cell adjacent to this heated surface are allowed to be indirectly heated. Warm wall CVD systems capable of depositing SiC epitaxy on several wafers simultaneously have emerged for commercial applications. Such systems have been described by Burk, Jr. (U.S. Pat. No. 5,954,881), Jurgensen, et. al., (WO 2002018670), and Hecht, et. al., (Materials Science Forum Vols. 645-648 (2010) pp. 89-94).
Defects in SiC are known to limit or destroy operation of semiconductor devices formed over the defects. Neudeck and Powell reported that hollow core screw dislocations (micropipes) severely limited voltage blocking performance in SiC diodes (P. G. Neudeck and J. A. Powell, IEEE Electron Device Letters, vol. 15, no. 2, pp. 63-65, (1994)). Neudeck reviewed the impact of crystal (wafer) and epitaxy originated defects on power devices in 1994, highlighting limitations of power device function due to screw dislocations and morphological epitaxy defects (Neudeck, Mat. Sci. Forum, Vols. 338-342, pp. 1161-1166 (2000)). Hull reported shift to lower values in the distribution of high voltage diode reverse bias leakage current when the diodes were fabricated on substrates having lower screw dislocation density (Hull, et. al., Mat. Sci. forum, Vol. 600-603, p. 931-934 (2009)). Lendenmann reported forward voltage degradation in bipolar diodes was linked to basal plane dislocations in the epilayer that originate from basal plane dislocations in the substrate (Lendenmann et. al., Mat. Sci. Forum, Vols. 338-342, pp. 1161-1166 (2000)).
3. Problem Statement
Advances in SiC substrate and epitaxy are required in order to reduce the concentration of defects that impact device operation and fabrication yields. Currently, defects formed on the surface of the substrate during SiC CVD epitaxy are the most influential defect impacting operation and yields of semiconductor devices on SiC substrates. In particular, SiC power devices which are required to handle large current (>50 A) with low on resistance are made using relatively large die sizes, greater than 7 mm per side. To achieve good manufacturing yield of these devices, methods to further reduce CVD epitaxy originated defects need to be developed. Solutions of these problems must also be capable of producing repeatable and consistent deposition of films that are smooth, uniform in thickness and electrical properties so that these parameters are still consistent with high device fabrication yields.
In multi-wafer, warm wall SiC CVD systems, reactant gas is introduced to a graphite reaction zone in the center of the system, the gas flow fans out in the radial direction and parallel to the substrate surface, and is finally evacuated at the periphery of the chamber. The floor of the reaction zone, or susceptor, contains the substrates and is actively heated, making it the hottest point in the reaction zone. Heating of the susceptor may be done using RF induction techniques or by resistive heaters. The adjacent surfaces are indirectly heated by the susceptor at the bottom of the chamber, and are at lower temperatures than the temperature target of the susceptor. Due to the control temperatures required for SiC CVD epitaxy, the reaction cell is constructed from graphite. Prior to its use, the parts of the reaction zone are often coated with pyrocarbon or tantalum carbide films which act as barriers to the out diffusion of impurities from the graphite. During CVD, ancillary deposits of SiC rapidly grow on the adjacent surfaces at a rate faster than the susceptor/substrate surface. Often, a mask, such as plates of polycrystalline SiC, can be laid over the uncovered regions of the susceptor to mask or protect areas of the susceptor from ancillary deposits. When these ancillary deposits reach a critical thickness, they will shed particles onto the substrates, resulting in defects in the epitaxial film that will impair operation of semiconductor devices. In addition, the formation of ancillary deposits consumes process gas reactant which can lead to run-to-run variations in film properties, film surface morphology, and particularly electrical properties.